The present invention relates to multi-protocol data communication switching and, more particularly, to methods and devices for facilitating protocol translations performed on discrete information units received on an input port in a first data communication protocol for transmission on an output port in a second data communication protocol, wherein the first and second protocols may be different.
Data communication switches transfer discrete information units between communication protocol domains. Where the source and destination protocol domains run different protocols, the switches must translate discrete information units into the protocol type operative in the destination protocol domain before forwarding can proceed. Protocol translation typically requires conversion of the inbound discrete information units to eliminate incompatibilities in the unit formats specified in the source and destination protocol domains. Examples of format incompatibilities include differences in unit header and/or trailer requirements and the maximum unit length. These or other incompatibilities may create the need to xe2x80x9cfragmentxe2x80x9d the inbound discrete information unit into multiple outbound units and to reserve different byte lengths at the head and/or tail of the outbound units for unit headers and/or trailers. Conventional switches have relied heavily on central processing units (CPU) to resolve such incompatibilities. However, this substantial CPU reliance has often introduced intervening steps into the switching process which have caused latency and created additional queueing requirements. Switching efficiency has suffered as a result. Therefore, there is a need for methods and devices for more efficiently conducting translational switching operations in a multi-protocol switching environment.
In its most basic feature, the present invention provides a translation hardware assist for resolving protocol incompatibilities in a multi-protocol switching environment. Discrete information units are transferred from inputs to disparate protocol outputs by writing inbound discrete information units into selected address spaces in allocated buffers in a manner which accounts for protocol format differences while allowing for straightforward dequeueing. The hardware assist fragments inbound discrete information units which violate a maximum unit length for the destination protocol type into multiple outbound units and creates explicit header offsets (and may create implicit trailer offsets) to accommodate the headers (and trailers) required for the destination protocol type. By selectively writing allocated buffers to account for protocol format differences, dequeueing can be accomplished by simply reading from the buffers first in, first out.
In a preferred embodiment, the destination address in an inbound discrete information unit is resolved to translation assist values, including a header offset value, maximum transfer unit value and segment size value. If the length of the discrete information unit does not exceed the resolved maximum transfer unit value, fragmentation is not indicated, and the discrete information unit is written using direct memory access (DMA) into one or more logically contiguous buffers, after skipping at the beginning of the first buffer a number of bytes corresponding to the resolved header offset value. If the length of a discrete information unit exceeds the resolved maximum transfer unit value, fragmentation is indicated, and the discrete information unit is fragmented into multiple segments corresponding to the resolved segment size value and transferred DMA into sets of one or more buffers each, after skipping before each segment a number of bytes corresponding to the resolved header offset value. Protocol-appropriate header/trailer information may be added to the residual spaces in the buffers to complete formation of the outbound discrete information units. The outbound discrete information units are eventually read DMA from the buffers in a predetermined logical order, such as first in, first out. A translational switching operation is therefore carried out seamlessly with the expedient of a straightforward hardware assist. The translation assist values may be stored in translation assist registers configured for each different protocol type operative in the switching environment which may be selectively consulted on a unit-by-unit basis through associative comparison with the destination addresses.
In another preferred embodiment, a bypass check is implemented which may further expedite the translation hardware assist. In the hardware assist with bypass mode, the largest header offset value for any protocol type operative in the switching environment is preselected and a bypass check based on the known or resolved protocol type of the inbound discrete information unit is performed. If the bypass check indicates that the inbound discrete information unit is of the protocol type which supports the shortest maximum transfer units relative to all other protocol types operative in the switching environment, it can be inferred that fragmentation of the inbound discrete information unit is not required and the discrete information unit is transferred DMA into one or more buffers after skipping a number of bytes corresponding to the preselected header offset value. If the bypass check indicates that the discrete information unit is not of the shortest maximum transfer unit protocol type operative in the switching environment, it can be inferred that fragmentation may be required. In that event, the header offset value, maximum transfer unit value and segment size value are resolved and the outbound discrete information unit is queued and dequeued as in the previous embodiment. Through the expedient of preselecting an offset value and performing the bypass check on inbound discrete information units, unnecessary fragmentation inquiries may be avoided.
These and other aspects of the present invention may be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings which are briefly described below. Of course, the actual scope of the invention is defined by the appended claims.